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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Block RAM and FIFO Switching Characteristics
Table 32: Block RAM and FIFO Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.9V
Units
-3
-2/-2L
-1
-1M
-2L
Block RAM and FIFO Clock-to-Out Delays
T RCKO_DO and
T RCKO_DO_REG (1)
Clock CLK to DOUT output
(without output register) (2)(3)
Clock CLK to DOUT output (with
1.57
0.54
1.80
0.63
2.08
0.75
2.08
0.75
2.44
0.86
ns, Max
ns, Max
output register) (4)(5)
T RCKO_DO_ECC and
T RCKO_DO_ECC_REG
Clock CLK to DOUT output with
ECC (without output
register) (2)(3)
Clock CLK to DOUT output with
2.35
0.62
2.58
0.69
3.26
0.80
3.26
0.80
4.49
0.94
ns, Max
ns, Max
ECC (with output register) (4)(5)
T RCKO_DO_CASCOUT and
T RCKO_DO_CASCOUT_REG
Clock CLK to DOUT output with
Cascade (without output
register) (2)
Clock CLK to DOUT output with
2.21
0.98
2.45
1.08
2.80
1.24
2.80
1.24
3.19
1.32
ns, Max
ns, Max
Cascade (with output register) (4)
T RCKO_FLAGS
T RCKO_POINTERS
T RCKO_PARITY_ECC
T RCKO_SDBIT_ECC and
T RCKO_SDBIT_ECC_REG
Clock CLK to FIFO flags
outputs (6)
Clock CLK to FIFO pointers
outputs (7)
Clock CLK to ECCPARITY in
ECC encode only mode
Clock CLK to BITERR (without
output register)
Clock CLK to BITERR (with
0.65
0.79
0.66
2.17
0.57
0.74
0.87
0.72
2.38
0.65
0.89
0.98
0.80
3.01
0.76
0.89
0.98
0.80
3.01
0.76
0.97
1.10
0.93
4.15
0.89
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
output register)
T RCKO_RDADDR_ECC and
T RCKO_RDADDR_ECC_REG
Clock CLK to RDADDR output
with ECC (without output
register)
Clock CLK to RDADDR output
0.64
0.71
0.74
0.79
0.90
0.92
0.90
0.92
0.98
1.10
ns, Max
ns, Max
with ECC (with output register)
Setup and Hold Times Before/After Clock CLK
T RCCK_ADDRA /T RCKC_ADDRA
T RDCK_DI_WF_NC /
T RCKD_DI_WF_NC
ADDR inputs (8)
Data input setup/hold time when
block RAM is configured in
WRITE_FIRST or NO_CHANGE
0.38/0.27
0.49/0.51
0.42/0.28
0.55/0.53
0.48/0.31
0.63/0.57
0.48/0.38
0.63/0.57
0.65/0.38
0.78/0.64
ns, Min
ns, Min
mode (9)
T RDCK_DI_RF /T RCKD_DI_RF
Data input setup/hold time when
block RAM is configured in
0.17/0.25
0.19/0.29
0.21/0.35
0.21/0.35
0.25/0.32
ns, Min
READ_FIRST mode (9)
T RDCK_DI_ECC /
T RCKD_DI_ECC
T RDCK_DI_ECCW /
T RCKD_DI_ECCW
T RDCK_DI_ECC_FIFO /
T RCKD_DI_ECC_FIFO
DIN inputs with block RAM ECC
in standard mode (9)
DIN inputs with block RAM ECC
encode only (9)
DIN inputs with FIFO ECC in
standard mode (9)
0.42/0.37
0.79/0.37
0.89/0.47
0.47/0.39
0.87/0.39
0.98/0.50
0.53/0.43
0.99/0.43
1.12/0.54
0.53/0.58
0.99/0.58
1.12/0.69
0.66/0.46
1.17/0.41
1.32/0.65
ns, Min
ns, Min
ns, Min
DS182 (v2.8) March 4, 2014
Product Specification
32
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